Field of the Invention
The present invention relates to an image processing apparatus for mutually converting a plurality of rectangular images and a raster image, a method of controlling same, and a storage medium.
Description of the Related Art
An image input unit such as for an image capturing apparatus of an image forming apparatus or an image output (forming) unit such as for an optical scanning apparatus typically handles image data in a raster scan order. In contrast, processing in units of rectangular images is performed in many digital image processes with respect to input data from an image input unit, for example filtering processing that uses a window, encoding processing for a JPEG method, a screening process for converting an input image that has been subjected to density tone representation into area coverage modulation, or the like. Below, processing in units of rectangular images is referred to as block processing, and an image order of a rectangular image unit handled in block processing is referred to as a block order.
To perform block processing with respect to an input image having a raster order, pre-processing for converting the image data of the input image into a block order becomes necessary. In this pre-processing, normally a line memory having a capacity of a rectangular area of the image width×the block height (the block area) is used. Below, an image unit of this line memory capacity amount is referred to as a band, and a line memory is also referred to as a band memory. If an image processing unit for performing block processing is configured by a pipeline, in each image processing unit, pre-processing for converting a raster order to a block order becomes necessary. Accordingly, line memory in proportion to the number of image processing units becomes necessary, and circuit scale increases. To suppress an increase of the line memory, it is necessary to convert a raster order into a block order in advance before inputting an image to the image processing unit. Because of this, configuration may be such that each image processing unit always handles an input image as a block order, and there ceases to be a need to use line memory in proportion to the number of image processing units. A block order image output from the image processing unit is converted again to the raster order for outputting to an image forming unit.
In the mutual conversion of the raster order and the block order that is necessary in pre-processing and post-processing of the image processing unit, a double-buffer scheme that uses two line memories having a capacity for a rectangular area obtained from the image width and the block height is widely known. In the double-buffer scheme, by reading out image data after an order conversion from one line memory, while image data for before the order conversion is being written to the other line memory, it becomes possible to perform conversion processing while also suppressing a decrease of throughput. However, in the double-buffer scheme, there is a problem in that a required line memory capacity is large, leading to an increase of a circuit scale. To solve this problem, a single-buffer scheme that enables a conversion even with a configuration in which there is only one line memory, by multiplexing writing of image data before the conversion and reading out of image data after the conversion, is known. Japanese Patent Laid-Open No. 2008-112435 discloses a method that realizes an address calculation in the single-buffer scheme.
However, there is a problem as is recited below in the foregoing conventional technique. In the single-buffer scheme, by sequentially performing writing of a next pixel to a line memory address for which reading out of a pixel has completed, it is possible to realize conversion processing in half a line memory capacity in comparison to the double-buffer scheme. However, in the single-buffer scheme, by multiplexing access for writing and reading out with respect to a line memory, there is the problem that an address calculation becomes complicated. Accordingly, in the above conventional technique, two address patterns are prepared for a single buffer, and writing and reading out are performed while switching the address patterns. However, in such a method, restrictions in an image width and a block size are introduced. For example, for an input image having a different size to an address pattern prepared in advance, if padding control for adding dummy pixels is not performed, it is not possible to use the address pattern. As a result, there is a problem in that an address calculation for an added dummy pixel is necessary, complicating control, and introducing a decrease in throughput.